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GS82582T20/38ge-550/500/450/400 288mb sigmaddr-ii+ tm burst of 2 sram 550 mhz?400 mhz 1.8 v v dd 1.8 v or 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.04 4/2016 1/26 ? 2012, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? 2.5 clock latency ? simultaneous read and write sigmaddr tm interface ? jedec-standard pinout and package ? double data rate interface ? byte write controls sampled at data-in time ? burst of 2 read and write ? on-die termination (odt) on data (d), byte write ( bw ), and clock (k, k ) inputs ? 1.8 v +100/C100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? data valid pin (qvld) supp ort ? ieee 1149.1 jtag-compliant boundary scan ? rohs-compliant 165-bump bga package sigmaddr-ii ? family overview the GS82582T20/38ge are built in compliance with the sigmaddr-ii+ sram pinout standard for common i/o synchronous srams. they ar e 301,989,888-bit (288mb) srams. the GS82582T20/38ge sigmaddr-ii+ srams are just one element in a family o f low power, low voltage hstl i/o srams designed to opera te at the speeds needed to implement economical high perf ormance networking systems. clocking and addressing schemes the GS82582T20/38ge sigmaddr-ii+ srams are synchronous devices. they empl oy two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. each internal read and write operatio n in a sigmaddr-ii+ b2 ram is two times wider than the device i/o bus. an input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. an output data multiplexer is used to cap ture the data produced from a single memory array read and th en route it to th e appropriate output drivers as needed. ther efore, the addre ss field of a sigmaddr-ii+ b2 ram is alway s one address pin less than the advertised index depth (e .g., the 16m x 18 has an 8m addressable index). parameter synopsis -550 -500 -450 -400 tkhkh 1.81 ns 2.0 ns 2.2 ns 2.5 ns tkhqv 0.45 ns 0.45 ns 0.45 ns 0.45 ns
8m x 36 sigmaddr- ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w bw2 k bw1 ld sa sa cq b nc dq27 dq18 sa bw3 k bw0 sa sa nc dq8 c nc nc dq28 v ss sa nc sa v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa qvld sa sa nc dq9 dq0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch note: bw0 controls writes to dq0:dq8; bw1 controls writes to dq9:dq17; bw2 controls writes to dq18:dq26; bw3 controls writes to dq27:dq35. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 2/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400
16m x 18 sigmaddr-ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w bw1 k sa ld sa sa cq b nc dq9 nc sa sa k bw0 sa nc nc dq8 c nc nc nc v ss sa nc sa v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa qvld sa sa nc nc dq0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch note: bw0 controls writes to dq0:dq8; bw1 controls writes to dq9:dq17. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 3/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400
pin description table symbol description type comments sa synchronous address inputs input ? r/ w synchronous read/write input high: read low: write bw0 ? bw3 synchronous byte writes input active low ld synchronous load pin input active low k input clock input active high k input clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? mcl must connect low ? ? dq data i/o input/output three state doff disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.8 v or 1.5 v nominal v ss power supply: ground supply ? qvld q valid output output ? odt on-die termination input active high nc no connect ? ? specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 4/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 notes: 1. nc = not connected to die or any other pin 2. when zq pin is directly connected to v ddq , output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. k and k cannot be set to v ref voltage.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 5/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 background common i/o srams, from a system architecture point of view, are attractive in read dominated or block transfer applications. therefore, the sigmaddr-ii+ sram interface and truth table are optimized for burst reads and writes. common i/o srams are unpopular in applications where a lternating reads and writes ar e needed because bus turnaroun d delays can cut high speed common i/o sram data bandwidth in half. burst operations read and write operations are "burst" operations. in every case where a read or write command is accepted by the sram, it will respond by issuing or accepting tw o beats of data, executing a data transfer on subsequent rising edges of k and k , as illustrated in the timing diagrams. this means th at it is possible to load new addresses every k clock cycle. addresses can be loaded less of ten, if intervening deselect cycles are inserted. deselect cycles chip deselect commands are pipe lined to the same degree as read commands. this means that if a deselect command is applied to the sram on the next cycle after a read command captured by the sram, the device will complete the two beat read data transfer and then execute the deselect c ommand, returning the output dri vers to high-z. a high on the ld pin prevents the ram from loading read or write command inpu ts and puts the ram into dese lect mode as soon as i t completes all outstanding burst transfe r operations. sigmaddr-ii+ burst of 2 sram read cycles the sram executes pipelined read s. the status of the address, ld and r/ w pins are evaluate d on the rising e dge of k. the read command ( ld low and r/ w high) is clocked into the s ram by a rising edge of k. sigmaddr-ii+ burst of 2 sram write cycles the status of the address, ld and r/ w pins are evaluated on the rising edge of k. the sram executes "late write" data transfers. data in is due at the device inputs on the rising edge of k fol lowing the rising edge of k clock used to clock in the write co mmand ( ld and r/ w low) and the write address. to complete the rem aining beat of the burst of two write tran sfer, the sram captures data in on the next rising edge of k , for a total of two tra nsfers per address load. special functions byte write control byte write enable pins are sampled at the same time that data i n is sampled. a high on the byte write enable pin associated wi th a particular byte (e.g., bw0 controls d0Cd8 inputs) will inh ibit the storage of that partic ular byte, leaving wh atever data may be stored at the current address at that byte location undisturbed. any or all of the byte write enable pins may be driven high o r low during the data in sample times in a write sequence. each write enable command and wr ite addres s loaded into the ram provides the base address for a 2-beat data transfer. the x18 version of the ram, for example, may write 36 bits in associati on with each address loaded. any 9-bit byte may be masked in an y write sequence. resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 3 d0?d8 byte 4 d9?d17 written unchanged unchanged written beat 1 beat 2
example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 6/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 flxdrive-ii output driver impedance control hstl i/o sigmaddr-ii+ srams are supplied with programmable impedance output drivers. the zq pin must be connected to v ss via an external resistor, rq, t o allow the sram to monitor and adjust its output driver impeda nce. the value of rq must be 5x the value of the desired ram output impedance. the allowable range of rq to guarantee impedance matching continuously is between 175 ? and 350 ? . periodic readjustment of the out put driver impedance is neces sary as the impedance is affected by drifts in supply voltage and temperatu re. the srams output impedance circuitry compensates for drifts in supply voltage and temperature. a clock cycle count er periodically triggers an impedance evaluation, resets and counts again. each impedance evaluation may move the output d river impedance level one step at a time towards the optimum l evel. the outp ut driver is implemented with discrete bina ry weighted impedance steps. input termination impedance control these sigmaddr-ii+ sra ms are supplied with programmable input t ermination on data (dq), byte write ( bw ), and clock (k, k ) input receivers. input termination can be enabled or disabled via the odt pin (6r). when the odt pin is tied low (or left floatingCthe pin has a small pull-down resistor), input termina tion is disabled. when the odt pin is tied high, input termina tion is enabled. termination impedance is programmed via the same rq r esistor (connected betw een the zq pin and v ss ) used to program output driver impedance , and is nominally rq*0.6 theven in-equivalent when rq is between 175 ? and 250 ? . periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manne r as for driver impedance (see above). notes: 1. when odt = 1, byte write ( bw ), and clock (k, k ) input termination is always enabled. consequently, bw , k, k inputs should always be driven high or low; they should never be tri -stated (i.e., in a high-z state ). if the inputs are tri-stated , the input termination will pull the signal to v ddq /2 (i.e., to the switch point of the dif f-amp receiver), which could cause the receiver to enter a meta-stable state, resulting in the receive r consuming more power than it normally would. this could resul t in the devices operati ng currents being higher. 2. when odt = 1, dq input termina tio n is enabled during write an d nop operations, and disabl ed during read operations. specifically, dq input terminatio n is disabled 0.5 cycles befor e the sram enables its dq drivers and starts driving valid read data, and remains disabled until 0.5 cycles after the sram stop s driving valid read d ata and disables i ts dq drivers; dq input termination is enabled at all other times. consequently, the sram controller should disa ble its dq input termination, enable its dq drivers, and drive dq inputs (high or low) during write and nop operations. and, it should enable its dq input termination and disable it s dq drivers during read operations. care should be taken during write or nop -> read transitions, and during read -> nop transitions, to minimize th e time during which one devi ce (sram or sram controller) has enabled its dq input termination while the other device has not yet enabled its dq driver. otherwise, the input terminatio n will pull the signal to v ddq /2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta- stable state, resulting in the r eceiver consuming more power th an it normally would. this could result in the devices operati ng currents being higher.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 7/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 power-up initialization $iwhusrzhuxsvwdeohlqsxwforfnvpxvwehdssolhgwrwkhghyl fhiru p vsulruwrlvvxlqjuhdgdqgzulwhfrppdqgv6hhwkhw .,qlw wlplqjsdudphwhulqwkh $&(ohfwulfdo&kdudfwhulvwlfv vhfwlrq 1rwh 7khw .,qlw uhtxluhphqwlvlqghshqghqwriw khw/rfnuhtxluhphqwzklfkvsh flilhvkrzpdq\f\fohvrivwdeohlqsxwforfnv pxvwehdssolhgdiwhuwkh 'rii slqkdvehhqgulyhq+ljklqrughu wrhqvxuhwkdwwkh'//orfnv surshuo\dqgwkh'//pxvworfn surshuo\ehiruhlvvxlqjuhdgd qgzulwhfrppdqgv+rzhyhuw .,qlw lvjuhdwhuwkdqw ./rfn hyhqdwwkhvorzhvw shuplwwhgf\fohwlph riqv qv p v&rqvhtxhqwo\wkh p vdvvrfldwhgzlwkw .,qlw lvvxiilflhqwwrfryhuwkhw ./rfn uhtxluhphqwdw srzhuxsliwkh 'rii slqlvgulyhq+ljksulruwrwkhvwduwriwkh p vshulrg $ovrw .,qlw rqo\qhhgvwrehphwrqfhlpphg ldwho\diwhusrzhuxszkhuhdv w ./rfn pxvwehphwdq\wlphwkh'//lvglvdeohguhvhw zkhwkhue\wrjjolqj 'rii /rzrue\vwrsslqj. forfnviru!qv
common i/o sigmaddr-ii+ burs t of 2 sram truth table k n ld r/ w dq operation a + 0 a + 1 ? 1 x hi-z / * hi-z / * deselect ? 0 0 d@k n+1 d@ k n+1 write ? 0 1 q@ k n+2 q@k n+3 read notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v ? = input ?valid?; ?x? = inpu t ?don?t care?. 2. d1 and d2 indicate the first and second pieces of w rite data transferred during write operations. 3. q1 and q2 indicate the first and second pieces of read data tra nsferred during read operations. 4. when on-die termination is disabled (odt = 0), dq drivers are disabl ed (i.e., dq pins are tri-st ated) for one cycle in respon se to nop and write commands, 2.5 cycles after the command is sampled. 5. when on-die termination is enabled (odt = 1), dq drivers ar e disabled for one cycle in response to nop and w rite commands, 2. 5 cycles after the command is sampled. the state of the dq pins during that time (denoted by ?*? in the table above) is determine d by the state of the dq input termination. see the input termination impedance control section for more information. burst of 2 byte write clock truth table bw bw current operation d d k ? (t n + 1 ) k ? (t n + 1? ) k ? (t n ) k ? (t n + 1 ) k ? (t n + 1? ) t t write dx stored if bwn = 0 in both data transfers d1 d2 t f write dx stored if bwn = 0 in 1st data transfer only d1 x f t write dx stored if bwn = 0 in 2nd data transfer only x d2 f f write abort no dx stored in either data transfer x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 8/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400
x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 9/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( ? 2.9 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( ? 2.9 v max.) v v tin input voltage (tck, tms, tdi) ?0.5 to v ddq +0.5 ( ? 2.9v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 10/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 ? v dd v reference voltage v ref v ddq /2 ? 0.05 ? v ddq /2 + 0.05 v note: . the power supplies need to be powered up simult aneously or in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . for more information, read an1021 sigmaquad and sigmaddr power-up. operating temperature parameter symbol min. typ. max. unit junction temperature (commercial range versions) t j 0 25 85 ?c junction temperature (industrial range versions)* t j ?40 25 100 ?c note: * the part numbers of industrial temperature range versions end with the character ?i?. unless otherwise noted, all performanc e specifications quoted are evaluated for worst case in the temperature range marked on the device.
thermal impedance package test pcb substrate ??ja (c/w) airflow = 0 m/s ? ja (c/w) airflow = 1 m/s ? ja (c/w) airflow = 2 m/s ??jb (c/w) ? jc (c/w) 165 bga 4-layer 16.10 13.69 12.73 6.54 2.08 notes: 1. thermal impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. please refer to jedec standard jesd51-6. 3. the characteristics of the test fixture pcb influence reported the rmal characteristics of the device. be advised that a good thermal path to the pcb can result in cooling or heating of the ram depending on pcb temperature. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 11/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 hstl i/o dc input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.05 v ddq /2 + 0.05 v ? input high voltage v ih1 v ref + 0.1 v ddq + 0.3 v 1 input low voltage v il1 ?0.3 v ref ? 0.1 v 1 input high voltage v ih2 0.7 * v ddq v ddq + 0.3 v 2,3 input low voltage v il2 ?0.3 0.3 * v ddq v 2,3 notes: 1. parameters apply to k, k , sa, dq, r/ w , bw , ld during normal operation and jtag boundary scan testing. 2. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 3. parameters apply to zq during jtag boundary scan testing only. hstl i/o ac input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.08 v ddq /2 + 0.08 v ? input high voltage v ih1 v ref + 0.2 v ddq + 0.5 v 1,2,3 input low voltage v il1 ?0.5 v ref ? 0.2 v 1,2,3 input high voltage v ih2 v ddq ? 0.2 v ddq + 0.5 v 4,5 input low voltage v il2 ?0.5 0.2 v 4,5 notes: 1. v ih(max) and v il(min) apply for pulse widths less than one-quarter of the cycle time. 2. input rise and fall times myust be a minimum of 1 v/ns, and within 10% of each other. 3. parameters apply to k, k , sa, dq, r/ w , bw , ld during normal operation and jtag boundary scan testing. 4. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 5. parameters apply to zq during jtag boundary scan testing only.
capacitance o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk v in = 0 v 5 6 pf note: this parameter is sample tested. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 12/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 ac test conditions parameter conditions input high level 1.25 v input low level 0.25 v max. input slew rate 2 v/ns input reference level 0.75 v output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. dq vt = v ddq /2 50? rq = 250 ?? (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua doff i il doff v in = 0 to v dd ?20 ua 2 ua odt i ilodt v in = 0 to v dd ?2 ua 20 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 13/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 hstl i/o output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 ? v 4, 5 output low voltage v ol2 ? 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175? ?? rq ? 275 ??? 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? ? rq ? 275 ?? . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v 4. 0 ???? rq ? ?? 5. i oh = ?1.0 ma 6. i ol = 1.0 ma
operating currents parameter symbol test conditions -550 -500 -450 -400 unit notes 0 to 70c C 40 to 85c 0 to 70c C 40 to 85c 0 to 70c C 40 to 85c 0 to 70c C 40 to 85c operating current (x36): ddr i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 1050 1070 960 980 870 890 790 810 ma 2, 3 operating current (x18): ddr i dd v dd = max, i out = 0 ma cycle time ?? t khkh min 980 1000 910 930 830 850 750 770 ma 2, 3 standby current (n op): ddr i sb1 device deselected, i out = 0 ma, f = max, all inputs ?? 0.2 v or ?? v dd ? 0.2 v 580 600 540 560 500 520 470 490 ma 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated with 5 0% read cycles and 50% write cycles. 4. standby current is only after all pending r ead and write burst operations are complete d. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 14/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 15/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 ac electrical characteristics parameter symbol -550 -500 -450 -400 units notes min max min max min max min max clock k, k clock cycle time t khkh 1.81 8.4 2.0 8.4 2.2 8.4 2.5 8.4 ns tk variable t kvar ? 0.15 ? 0.15 ? 0.15 ? 0.2 ns 4 k, k clock high pulse width t khkl 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k, k clock low pulse width t klkh 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k to k high t kh k h 0.77 ? 0.85 ? 0.94 ? 1.06 ? ns k to k high t k hkh 0.77 ? 0.85 ? 0.94 ? 1.06 ? ns dll lock time t klock 2048 ? 2048 ? 2048 ? 2048 ? cycle 5 k static to dll reset t kreset 30 ? 30 ? 30 ? 30 ? ns k, k clock initialization t kinit 20 ? 20 ? 20 ? 20 ? p s 6 output times k, k clock high to data output valid t khqv ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k, k clock high to data output hold t khqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns k, k clock high to echo clock valid t khcqv ? 0.29 ? 0.33 ? 0.37 ? 0.45 ns k, k clock high to echo clock hold t khcqx ?0.29 ? ?0.33 ? ?0.37 ? ?0.45 ? ns cq, cq high output valid t cqhqv ? 0.15 ? 0.15 ? 0.15 ? 0.2 ns cq, cq high output hold t cqhqx ?0.15 ? ?0.15 ? ?0.15 ? ?0.2 ? ns cq, cq high to qlvd t qvld ?0.15 0.15 ?0.15 0.15 ?0.15 0.15 ?0.2 0.2 ns cq phase distortion t cqh cq h t c q hcqh 0.655 ? 0.75 ? 0.85 ? 1.0 ? ns k clock high to data output high-z t khqz ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k clock high to data output low-z t khqx1 ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns setup times address input setup time t avkh 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns 1 control input setup time ( rw , ld ) t ivkh 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns 2 control input setup time ( bwx ) t ivkh 0.18 ? 0.2 ? 0.22 ? 0.28 ? ns 3 data input setup time t dvkh 0.18 ? 0.2 ? 0.22 ? 0.28 ? ns hold times address input hold time t khax 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns 1 notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control signals are rw , ld . 3. control signals are bw0 , bw1 and ( bw2 , bw3 for x36). 4. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 5. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 6. after device power-up, 20 p s of stable input clocks (as specified by t kinit ) must be supplied before reads and writes are issued.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 16/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 control input hold time ( rw , ld ) t khix 0.23 ? 0.25 ? 0.275 ? 0.4 ? ns 2 control input hold time ( bwx ) t khix 0.18 ? 0.2 ? 0.22 ? 0.28 ? ns 3 data input hold time t khdx 0.18 ? 0.2 ? 0.22 ? 0.28 ? ns ac electrical character istics (continued) parameter symbol -550 -500 -450 -400 units notes minmaxminmaxminmax min max notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control signals are rw , ld . 3. control signals are bw0 , bw1 and (bw2 , bw3 for x36). 4. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 5. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 6. after device power-up, 20 p s of stable input clocks (as specified by t kinit ) must be supplied before reads and writes are issued.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 17/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 read-write k-based timing diagram noop read noop noop write read read noop noop write write a1 a2 a3 a4 a5 a6 d d d d tqvld tqvld tdvkh tkhdx tkhqv tkhqx tkhqx tkhqv tkhdx tdvkh tkhz tkhqx tklz tkhix tivkh tkhix tivkh tkhax tavkh k k addr ld w r/ qvld dq cq cq
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 18/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 read-write cq-based timing diagram noop read noop noop write read read noop noop write write a1 a2 a3 a4 a5 a6 q1 q1+1 d2 d2+1 q3 q3+1 q4 q4+1 d5 d5+1 d6 tcqhqx tcqlqv tcqhqv tcqlqx tcqlqx tqvld tcqhqv tcqlqv tcqhqx tqvld tdvkh tkhdx tkhdx tdvkh tkhix tivkh tkhix tivkh tkhax tavkh k k addr ld w r/ dq cq cq qvld
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 19/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 jtag port operation overview the jtag port on this ram operate s in a manner th at is complian t with ieee standard 1149.1-1 990, a serial boundary scan interface standard (commonly refe rred to as jtag). the jtag por t input interface le vels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device w ithout utilizing the jtag po rt. the port is reset at power-up and will remai n inactive unle ss clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal opera tion of the ram with the jtag port unused, tck, tdi, and tms ma y be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the fa lling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state m achine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed b etween tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the fa lling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag regist ers, refered to as t es t access port or t ap registers, are selected (one a t a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register t hat captures serial input data on the rising edge of tck and pushes serial data out on the next fall ing edge of tck. when a register is selected, it is placed betw een the tdi and tdo pins. instruction register the instruction register holds the instructions that are execut ed by the tap controller when it is moved into the run, test/id le, or the various data register states . instructions are 3 bits long. the instruction register can be loaded when it i s placed between the tdi and tdo pins. the instruction register is automatically pre loaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed b etween tdi and tdo. it allows serial test data to be passed t hrough the rams jtag port to anothe r device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a co llection of flip flops that c an be preset by the logic level found on the rams input or i/o pins. the flip flops are then daisy ch ained together so the levels fo und can be shifted serially out o f the jtag ports tdo pin. th e boundary scan register also incl udes a number of place holder flip flops (always set to a logi c 1). the relationship between the device pins and the bits in the boundary scan register is descr ibed in the scan ord er table following. the boundary scan
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 20/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 register, under the control of t he tap controller, is loaded wi th the contents of the rams i/o r ing when the controller is in capture-dr state and then is placed between the tdi and tdo pin s when the controller is moved to shift-dr state. sample-z, sample/preload and extest instruct ions can be used to activate the boundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 12 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a devi ce and ven dor specific 32-bit code when the controller is put i n capture-dr state with the idcode command loaded in the instruct ion register. the code is load ed from a 32-bit on-chip rom. it describes various attributes o f the ram as indicated below. the register is then placed betw een the tdi and tdo pins when t he controller is moved into shift-dr state. bit 0 in the register is the lsb and the f irst to reach tdo when shifting begins. id register contents see bsdl model gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 21/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 tap controller instruction set overview there are two classes of in structions defined in the standard 1 149.1-1990; the standard (public) instructions, and device spec ific (private) instructions. some publ ic instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. t he tap on this device may be u sed to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in c apture-ir state the two l east significant bits of the inst ruction register are loaded wi th 01. when the controller is moved to the shift-ir state the instruct ion register is placed between tdi and tdo. in this state the d esired instruction is serially loaded t hrough the tdi input (while the previous contents are shifted out at tdo). for all instruction s, the tap executes newly loaded instructions only when the controller is moved to update-ir state. th e tap instruction set for this device is listed in the following table. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction regist er the bypass register is placed between tdi and tdo. this occurs when the tap co ntroller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other dev ices in the scan path.
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 22/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 sample/preload 6$03/(35(/2$'lvd6wdqgdugpdqgdwru\sxeolflqvwuxfwlr q:khqwkh6$03/(35(/2$'lqvwuxfwlrqlv ordghglqwkh,qvwuxfwlrq5hjlvw huprylqjwkh7$3frqwuroohul qwrwkh&dswxuh'5vwdwhordgvw khgdwdlqwkh5$0vlqsxwdqg ,2exiihuvlqwrwkh%rxqgdu\6fdq5hjlvwhu%rxqgdu\6fdq5hjl vwhuorfdwlrqvduhqrwdvvrfldwhgzlwkdqlqsxwru,2slqdqg duhordghgzlwkwkhghidxowvwdw hlghqwlilhglqwkh%rxqgdu\6f dq&kdlqwdeohdwwkhhqgriwklvvhfwlrqriwkhgdwdvkhhw%hf dxvh wkh5$0forfnlvlqghshqghqwiurpwkh7$3&orfn7&.lwlvsrv vleohiruwkh7$3wrdwwhpswwrfdswxuhwkh,2ulqjfrqwhqwv zklohwkhlqsxwexiihuvduhlqw udqvlwlrqlhlqdphwdvwdeoh vwdwh$owkrxjkdoorzlqjwkh7$3wrvdpsohphwdvwdeohlqsxwv zloo qrwkdupwkhghylfhu hshdwdeohuhvxowvfdq qrwehh[shfwhg5$0 lqsxwvljqdovpxvwehvwdelol]hgiruorqjhqrxjkwrphhwwkh 7$3vlqsxwgdwdfdswxuhvhwxsso xvkrogwlphw76 soxvw7+7 kh5$0vforfnlqsxwvqhhgqrw ehsdxvhgirudq\rwkhu7$3 rshudwlrqh[fhswfdswxulqjwkh,2ulqjfrqwhqwvlqwrwkh%rxqg du\6fdq5hjlvwhu0rylqjwkhf rqwuroohuwr6kliw'5vwdwhwkhq sodfhvwkherxqgdu\vfdquhjlvwhu ehwzhhqwkh7',dqg7'2slqv extest (;7(67lvdq,(((pdqgdwru\sxeolflqvwuxfwlrq,wlvwr ehh[hfxwhgzkhqhyhuwkhlqvwu xfwlrquhjlvwhulvordghgzlwk dooorjlfv7kh(;7(67frppdqg grhvqrweorfnruryhuulghwkh 5$0?vlqsxwslqvwkhuhiruhwkh5$0?vlqwhuqdovwdwhlv vwlooghwhuplqhge\lwvlqsxwslqv 7\slfdoo\wkh%rxqgdu\ 6fdq5hjlvwhulvordghgzlwkwkhghvluh gsdwwhuqrigdwdzlwkwkh6$03/(35(/2$'frppdqg 7khqwkh(;7(67frppdqglvxvhg wrrxwsxwwkh%rxqgdu\6fdq5hj lvwhu?vfrqwhqwvlqsdudoohorqwkh5$0?vgdwdrxwsxw gulyhuvrqwkhidoolqj hgjhri7&.zkhqwkhfrqwuroohulvlqwk h8sgdwh,5vwdwh $owhuqdwho\wkh%rxqgdu\6fdq5hjlvwhupd\ehordghglqsdudoo hoxvlqjwkh(;7(67frppdq g:khqwkh(;7(67lqvwuxf wlrqlvvhohfwhgwkhvdwhridoowkh5$0?vlqsxwdqg,2slqv dvzhoodvwkhghidxowydoxhvd w6fdq5hjlvwhuorfdwlrqvqrwd vvr fldwhgzlwkdslqduh wudqvihuuhglqsdudooholqwrwkh%rxqgdu \6fdq5hjlvwhurqwkhulvlqjhg jhri7&.lqwkh&dswxuh'5 vwdwhwkh5$0?vrxwsxwslqvgulyhrxwwkhydoxhriwkh%rxqgdu \6fdq5hjlvwhuorfdwlrqzlwkz klfkhdfkrxwsx wslqlvdvvrfl dwhg idcode 7kh,'&2'(lqvwuxfwlrqfdxvhvwkh,'520wrehordghglqwrwkh ,'uhjlvwhuzkhqwkhfrqwuroohulvlq&dswxuh'5prghdqg sodfhvwkh,'uhjlvwhuehwzhhqw kh7',dqg7'2slqvlq6kliw'5 prgh7kh,'&2'(lqvwuxfwlrq lvwkhghidxowlqvwuxfwlrq ordghglqdwsrzhuxsdqgdq\w lphwkhfrqwuroohulvsodfhglq wkh7hvw/rjlf5hvhwvwdwh sample-z ,iwkh6$03/(=lqvwuxfwlrqlvo rdghglqwkhlqvwuxfwlrquhjlvw hudoo5$0rxwsxwvduhirufhgwr dqlqdfwlyhguly hvwdwhkljk =dqgwkh%rxqgdu\6fdq5hjlvwh ulvfrqqhfwhgehwzhhq7',dqg 7'2zkhqwkh7$3frqwuroohu lvpryhgwrwkh6kliw'5 vwdwh
jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 gsi 011 gsi private instruction. 1 sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 gsi 110 gsi private instruction. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 23/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj C 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.7 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj C 300 1 ua 2 tms, tck and tdi input leakage current i inlj C 1 100 ua 3 tdo output leakage current i olj C 1 1 ua 4 test port output high voltage v ohj v dd ? 0.2 v 5, 6 test port output low voltage v olj 0.2 v 5, 7 test port output cmos high v ohjc v dd ? 0.1 v 5, 8 test port output cmos low v oljc 0.1 v 5, 9 notes: 1. input under/overshoot voltage must be C 1 v < v i < v ddn +1 v not to exceed v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj ? v in ?? v ddn 3. 0 v ?? v in ?? v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v dd supply. 6. i ohj = C 2 ma 7. i olj = + 2 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua
notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 tdo v dd /2 50? 30pf * jtag port ac test load * distributed test jig capacitance specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 24/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 25/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400 package dimensions?165-bu mp fpbga (package ge) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 150.05 170.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.15 c 0.36~0.46 1.50 max.
ordering information gs i sigmaddr-ii+ sram org part number 1 type package speed (mhz) t j 2 16m x 18 GS82582T20ge-550 sigmaddr-ii+ sram rohs-compliant 165-bump bga 550 c 16m x 18 GS82582T20ge-500 sigmaddr-ii+ sram rohs-compliant 165-bump bga 500 c 16m x 18 GS82582T20ge-450 sigmaddr-ii+ sram rohs-compliant 165-bump bga 450 c 16m x 18 GS82582T20ge-400 sigmaddr-ii+ sram rohs-compliant 165-bump bga 400 c 16m x 18 GS82582T20ge-550i sigmaddr-ii+ sram rohs-compliant 165-bump bga 550 i 16m x 18 GS82582T20ge-500i sigmaddr-ii+ sram rohs-compliant 165-bump bga 500 i 16m x 18 GS82582T20ge-450i sigmaddr-ii+ sram rohs-compliant 165-bump bga 450 i 16m x 18 GS82582T20ge-400i sigmaddr-ii+ sram rohs-compliant 165-bump bga 400 i 8m x 36 gs82582t38ge-550 sigmaddr-ii+ sram rohs-compliant 165-bump bga 550 c 8m x 36 gs82582t38ge-500 sigmaddr-ii+ sram rohs-compliant 165-bump bga 500 c 8m x 36 gs82582t38ge-450 sigmaddr-ii+ sram rohs-compliant 165-bump bga 450 c 8m x 36 gs82582t38ge-400 sigmaddr-ii+ sram rohs-compliant 165-bump bga 400 c 8m x 36 gs82582t38ge-550i sigmaddr-ii+ sram rohs-compliant 165-bump bga 550 i 8m x 36 gs82582t38ge-500i sigmaddr-ii+ sram rohs-compliant 165-bump bga 500 i 8m x 36 gs82582t38ge-450i sigmaddr-ii+ sram rohs-compliant 165-bump bga 450 i 8m x 36 gs82582t38ge-400i sigmaddr-ii+ sram rohs-compliant 165-bump bga 400 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number . ? example: gs82582t38ge-400t. 2. c = commercial temperature range. i = industrial t emperature range. sigmaddr-ii+ sram revision history file name format/content description of changes 82582txxe_r1 ? creation of datasheet 82582txxe_r1_01 content ? updated speed bin offerings 82582txxe_r1_02 content ? removed x8 and x9 configurations 82582txxe_r1_03 content ? removed leaded part numbers ? added power-up initialization section on page 10 ? added tkinit specification 82582txxe_r1_04 content ? removed preliminary banner ? added op current cz data specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04 4/2016 26/26 ? 2012, gsi technology GS82582T20/38ge-550/500/450/400

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